Fully parallel comparator for the moduli set {2n, 2n-1, 2n+1}
نویسندگان
چکیده
A novel circuit based on sign detection is introduced in this paper which uses the subtraction for comparing two numbers without carrying out a full comparison and conversion. Thus, the proposed schema decreases the delay significantly using only a little redundant hardware in contrast to previous works. Also the time complexity of the new design has the best results comparing to the previous work.
منابع مشابه
Overflow Detection in Residue Number System, Moduli Set {2n-1,2n,2n+1}
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ورودعنوان ژورنال:
- IEICE Electronic Express
دوره 8 شماره
صفحات -
تاریخ انتشار 2011